Discussion Question: CISC vs RISC

Computer functionalities are tied to it instructions Set (ISA) implemented in it processor. But to be Turing-Complete, a computer must flexible enough to be able to compute anything actually computable. With Stored-Program architecture, also known as Van Neumann architecture, this flexibility has to be done by instructions (program) loaded in memory, only instructions(ISA) required to execute loaded (in memory) program are hardwired into the processor.

early 1960s and onwards, programs was mostly written in Assembly and computers architects tried to fill the semantic gap by designing Instruction Set combined into single instructions that will directly support High Level Language construct and reduce the size of program, main memory access. At this time this design was an important cost saving element. This design is called Complex Instruction Set Computer, due to complex Instruction Set being implemented into the processor.(Wikipedia) However, this design has several side effect, as complications instructions decoding and scheduling, wide variation of required number of clock(Dandamudi,2005,p39).

For these and other reasons, in the early 1980s designers started looking at simple Instruction Set Architecture that produce instruction sets with far fewer instructions and they coined as opposite to CISC the term Reduced Instruction Set Computer (RISC). Despite the term will induce, the RISC goal was not to reduce the number of instructions, but the complexity. (Dandamudi, Sivarama,2005,p39).

Difference between these Two architectures can be illustrated by the table from http://arstechnica.com

CISC	RISC
Performance Strategies
Complexity from software to hardware. Decreased code size, high Cycle Per Instruction.	Complexity from hardware to software Low Cycle Per Instruction, increased code size.
Design
Instructions for performing basic, complex, and multi-cycle tasks. Memory-to-memory addressing modes. Microcode control unit. Fewer register	Instructions that perform only basic functions.  Simple addressing modes. Register-to-Register Operations. Direct execution control unit. Many register Pipelined execution to lower CPI.

(Ars Technica, 2004)

Even if, since initial research and subsequent commercialisation in the late 1970s and early 1980s, RISC design has dominated the field of computer architecture, The widespread of CISC into desktop and server computing was more due to market share being hold by earlier x86 intel’s processor RISC design was very attractive for power server, mobile and embedded device.

To summarize, CISC originate from memory cost saving need and move instructions complexities to the hardware, but encounter several performance issues sorted out by RISC. With today technologies, CISC are mainly kept for compatibility reason, but include many of solution provided by RISC. RISC is becoming more complex than before and using some of technique used to improve CISC. All these make the distinction between these two designs irrelevant. However, it should be noted that RISC still retain some important single-cycle instructions Register-to-register and load/store architecture and a large number of general purpose registers.

As stated by Michael S. Schlansker and B. Ramakrishna Rau, the computer industry has grown accustomed to, and take for granted, increase of microprocessor performance, without requiring a rewriting or recompiling of the program.(Schlansker and Ramakrishna,2000,p.1). Also the any future ISA must take this fact in account. One of the IAS that will replace CISC and RISC, could be based on parallel computing as Explicitly Parallel Instruction Computing from HP and Intel.

Reference List

• Ars Technica, (2004) RISC vs. CISC: the Post-RISC Era Available At: http://arstechnica.com/cpu/4q99/risc-cisc/rvc-5.html#Branch
• Brookshear, Computer Science an overview 10^th Edn. Addison-Wesley
• Page D.(2009) Practical Introduction to Computer Architecture, London : Springer London, 2009. Liverpool University Librairie
• Dandamudi, Sivarama P .(2005) Guide to RISC Processors for programmers and engineers, New York, NY : Springer Science+Business Media, Inc., 2005. Liverpool University Librairie
• Schlansker, M. S and Ramakrishna Rau(2000), EPIC: An Architecture for Instruction-Level Parallel Processors, HP [Online] Available at: http://www.hpl.hp.com/techreports/1999/HPL-1999-111.pdf.
• Wikipedia, (2011) Reduced instruction set computing Available at: http://en.wikipedia.org/wiki/Reduced_instruction_set_computing (Accessed:06-09-2011)
• Wikipedia, (2011) Complex instruction set computing Available at: http://en.wikipedia.org/wiki/Complex_instruction_set_computer (Accessed:06-09-2011)